One type of prior computer system comprises a microprocessor connected to an external cache, a system memory, and various peripheral devices residing on a system bus. The microprocessor communicates with the cache memory, system memory, and peripherals through a memory controller chip. The memory controller chip coordinates data transfers to and from these memory components at the request of the microprocessor. One example of a prior art memory controller chip is the 82434LX/NX PCI cache and Memory controller (PCMC), manufactured by Intel Corporation of Santa Clara, Calif., the corporate assignee of the present invention.
FIG. 1 illustrates a prior art computer system employing a memory controller chip. The microprocessor 110 is coupled to an external cache 120 and system memory 130 on a host bus 160. The host bus 160 is connected to a memory controller 140. A second bus, system bus 150, is connected to the memory controller 140. The memory controller 140 functions as a bridge between microprocessor 110 and the devices that are coupled to the system bus 150. For example, system bus may include devices such as a graphics accelerator, hard drive controller, and add-in boards.
The memory controller 140 handles data transfer requests from the microprocessor 110. The memory controller 140 receives the read or write request from the microprocessor 110 and determines which device is the data source or target. The microprocessor issues a read or write request using standard microprocessor timings.
One type of prior memory controller 140 includes a microprocessor interface (for communicating with the microprocessor), a cache controller (for communicating with the external cache), a system memory controller (for communicating with the system memory) and a bus controller (for communicating with the system bus). These functional components of the memory controller are included within one integrated circuit chip. Alternatively, some manufacturers split the functions among more than one chip.
The microprocessor interface unit of the memory controller receives, for instance, read commands from the microprocessor and determines (1) the "source", i.e. the device containing the requested data, and (2) at what address within the device the data is to be found. If the source is determined to be a device on the system bus, the bus controller takes over. If the source is determined to be system memory, the system memory controller takes over. Upon a request for a system memory read, the cache controller searches the cache for the requested data. If the desired read data is in the cache, there is a cache hit and the data is sent back to the microprocessor. The system memory controller senses the cache hit and does not proceed with the system memory read. This method of retrieving data from the cache improves computer system performance by reducing the amount of time it takes for the microprocessor to retrieve system memory data.
Although the system performance is improved by using an external cache, there is also a considerable time penalty associated with a system memory read that does not hit in the cache. For one example of a system memory comprising dynamic random access memory (DRAM), it takes 7 clocks to retrieve the first data word from system memory. However, if the microprocessor were to request two data words from system memory, it would take considerably less time (i.e. 2 clocks) to return the second data word.
Some prior art computer systems take advantage of this time savings by retrieving an entire line (four data words) from system memory during a read operation, whether or not the entire line was requested by the microprocessor. The entire line is then placed in the cache. For a computer system based on a Pentium.RTM. Processor manufactured by Intel Corporation of Santa Clara, Calif., each data word comprises 64 bits.
Thus it can be appreciated that in order to improve system performance during a system memory read, the number of clock cycles required to return a first data word from system memory should be reduced. It is therefore desirable to provide for a method by which system performance may be increased by decreasing the time required to retrieve a data word from system memory.